1. Technical Field
The present invention relates to digital circuits in general, and, in particular, to fused multiply-adder circuits. Still more particularly, the present invention relates to a low-latency low-power shift and negate unit within a fused multiply-adder circuit.
2. Description of Related Art
A floating-point unit is typically required to perform various mathematical operations on floating-point numbers. It is always useful to enhance the speed of floating-point functions and one known technique is to provide specialized hardware to implement certain floating-point functions. For example, a fused multiply-adder circuit can be used in a floating-point unit to perform multiply-accumulate functions that are commonly used in digital signal processing operations.
A fused multiply-adder circuit basically combines a multiplication operation with an add operation. Within a fused multiply-adder circuit, a multiplicand and a multiplier are initially multiplied via a partial product generation module. The partial products are then added by a partial product reduction module that reduces the partial products to a Sum and a Carry in their redundant form. The redundant Sum and Carry are further added to an addend via a carry-save adder to form a second redundant Sum and a second redundant Carry. The second redundant Sum and the second redundant Carry are subsequently added within a carry-propagate adder to yield a Sum Total.
The present disclosure provides a low-latency low-power shift-and-negate unit within a fused multiply-adder circuit.